The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
Photoresist materials are coated onto the surface of a wafer by dispensing a photoresist fluid typically on the center of the wafer as the wafer rotates at high speeds within a stationary bowl or coater cup. The coater cup catches excess fluids and particles ejected from the rotating wafer during application of the photoresist. The photoresist fluid dispensed onto the center of the wafer is spread outwardly toward the edges of the wafer by surface tension generated by the centrifugal force of the rotating wafer. This facilitates uniform application of the liquid photoresist on the entire surface of the wafer.
Spin coating of photoresist on wafers, as well as the other steps in the photolithographty process, is carried out in an automated coater/developer track system using wafer handling equipment which transport the wafers between the various photolithography operation stations, such as vapor prime resist spin coat, develop, baking and chilling stations. Robotic handling of the wafers minimizes particle generation and wafer damage. Automated wafer tracks enable various processing operations to be carried out simultaneously. Two types of automated track systems widely used in the industry are the TEL (Tokyo Electron Limited) track and the SVG (Silicon Valley Group) track.
During the photolithography step of semiconductor production, light energy is applied through a reticle mask onto the photoresist material previously deposited on the wafer to define circuit patterns which will be etched in a subsequent processing step to define the circuits on the wafer. A reticle is a transparent plate patterned with a circuit image to be formed in the photoresist coating on the wafer. A reticle contains the circuit pattern image for only a few of the die on a wafer, such as four die, for example, and thus, must be stepped and repeated across the entire surface of the wafer. In contrast, a photomask, or mask, includes the circuit pattern image for all of the die on a wafer and requires only one exposure to transfer the circuit pattern image for all of the dies to the wafer.
There are two basic types of photoresist: positive and negative. When positive photoresist is applied to a substrate, light energy ruptures bonds in the portion of the photoresist which covers the portion of the underlying metal to be removed by etching. Thus, the ruptured portions of the resist render the underlying metal vulnerable to etching while the portions which are not ruptured render the underlying metal resistant to etching. On the other hand, when negative photoresist is applied to a substrate, light energy cross-links the portion of the resist which is to mask or shield the underlying metal layer from etching. Thus, the portions of the resist which are not cross-linked render the underlying metal layer vulnerable to etching while the portions which are cross-linked render the underlying metal resistant to etching.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
A typical method of forming a circuit pattern on a wafer includes introducing the wafer into the automated track system and then spin-coating a photoresist layer onto the wafer. The photoresist is next cured by conducting a soft bake process. After it is cooled, the wafer is placed in an exposure apparatus, such as a stepper, which aligns the wafer with an array of die patterns etched on the typically chrome-sputtered quartz reticle. When properly aligned and focused, the stepper exposes a small area of the wafer, then shifts or “steps” to the next field and repeats the process until the entire wafer surface has been exposed to the die patterns on the reticle. The photoresist is exposed to light through the reticle in the circuit image pattern. Exposure of the photoresist to this image pattern cross-links and hardens the resist in the circuit pattern. After the aligning and exposing step, the wafer is exposed to post-exposure baking and then is developed and hard-baked to develop the photoresist pattern.
The circuit pattern defined by the developed and hardened photoresist is next transferred to the underlying metal conductive layer using a metal etching process, in which metal over the entire surface of the wafer and not covered by the photoresist with ruptured bonds is etched away from the wafer with the metal under the cross-linked photoresist that defines the circuit pattern protected from the etchant. As a result, a well-defined pattern of metallic microelectronic circuits which closely approximates the cross-linked photoresist circuit pattern remains in the metal layer.
Reticles and masks typically include a transparent substrate of silica glass or quartz on which is provided a thin chrome layer that is patterned to define the necessary design shapes of the circuitry for a particular layer on a wafer. The basic steps for forming or “writing” a circuit pattern on a mask or reticle are similar to the steps for transferring the circuit pattern photolithographically from the mask or reticle to the wafer and are summarized in FIGS. 1A-1D. As shown in FIG. 1A, a mask blank 8 includes a transparent substrate 10 which is silica glass or quartz, for example; a chrome layer 12 deposited on the substrate 10; and a positive photoresist 14 deposited on the chrome layer 12. As shown in FIG. 1B, a desired width of the photoresist 14 is subjected to an electron beam 18 to form photoresist 16 with ruptured bonds, the width of which corresponds to the critical dimension (CD) for the circuit pattern to be ultimately transferred to a wafer (not shown) using the mask 8. Eventually, as shown in FIG. 1D, the photoresist 16 with ruptured bonds and underlying portion of the chrome layer 12 is etched and the unexposed photoresist 14 is stripped to define a mask 24. A gap 26 which corresponds to the width of a device feature of the circuit pattern to be transferred to the wafer is thus etched in the chrome layer 12 of the mask 24. In subsequent photolithography steps, light energy is transmitted through the gap 26 and the transparent substrate 10 to a layer of photoresist (not shown) on the wafer to define the circuit pattern in the photoresist, with the areas of the photoresist which are exposed to the light energy through the gap 26 becoming cross-linked and the areas of the photoresist which are shielded by the chrome layer 12 remaining in the non cross-linked configuration.
After the photoresist 16 with ruptured bonds is formed on the substrate 10 and before the chrome layer 12 is etched, the mask blank 8 undergoes a post-exposure delay (PED) period, during which time the mask blank 8 is temporarily stored prior to photoresist development. As shown in FIG. 1C, during this waiting period, which is referred to as the “Q-time” and is typically about 2-24 hours, the photo-cracking photoresist 16 is exposed to atmospheric humidity and ammonium (NH4) ions in the clean room storage environment. This causes the photo-cracking photoresist 16 to become un-cross-linked at the junction between the unexposed photoresist 14 and the exposed, photo-cracking photoresist 16. Accordingly, the photo-cracking photoresist 16 gradually narrows from an intended width 22 that corresponds to the intended critical dimension for the device features of the circuit pattern to be formed, to an actual width 20 which may be 28 nm narrower than the intended width 22. The area of photoresist which is sensitive to etching has the narrowed, actual width 20 rather than the original, intended width 22. When that occurs, the width of the gap 26 subsequently etched in the chrome layer 12 corresponds to the actual width 20 rather than the intended width 22, as shown in FIG. 1D. This adversely affects the dimensions of device features which are ultimately fabricated on the wafer based on the circuit pattern transferred to photoresist on the wafer using the fabricated mask 24. It has been found that the photo-cracking photoresist may narrow by as much as 28 nanometers over a 24-hour post-exposure delay period. Accordingly, a novel composite layer structure method is needed for the fabrication of a circuit pattern in a mask to minimize post-exposure delay (PED) effects of mask fabrication.
An object of the present invention is to provide a novel composite layer method suitable for reducing post-exposure delay (PED) effects associated with fabricating a photolithography reticle or mask.
Another object of the present invention is to provide a novel composite layer method suitable for preventing or minimizing variations between intended and realized critical dimension values of circuit pattern features fabricated on photolithography masks.
Still another object of the present invention is to provide a novel composite layer method which stabilizes photoresist sensitivity during post-exposure delay (PED) periods.
Yet another object of the present invention is to provide a novel composite layer method which widens the available process window between cross-linking a photoresist layer on a mask blank typically by electron beam exposure and etching a chromium layer to define a circuit pattern on the mask.
A still further object of the present invention is to provide a novel composite layer method which includes providing a photoresist layer on a chromium layer of a mask blank, providing a protective layer on the photoresist layer and exposing the protective layer and the photoresist layer to an electron beam to photo-crack the photoresist layer, such that the protective layer prevents Q-time narrowing of the photo-cracking photoresist during post-exposure delay periods.
Still another object of the present invention is to provide a photolithography mask which is fabricated by providing a mask blank having a transparent substrate and a chromium layer provided on the substrate, providing a photoresist layer on the chromium layer, providing a protective layer on the photoresist layer, defining a circuit pattern in the photoresist layer by photo-cracking the photoresist layer, and etching the chromium layer according to the cross-linked photoresist to define the circuit pattern in the chromium layer.